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| RF2131 2 Typical Applications * AMPS/ETACS Cellular Handsets * CDPD Portable Data Cards * 900MHz ISM Band Equipment * Commercial and Consumer Systems * Portable Battery-Powered Equipment HIGH EFFICIENCY AMPS/ETACS AMPLIFIER 2 POWER AMPLIFIERS Product Description The RF2131 is a high-power, high-efficiency amplifier IC. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in AMPS and ETACS handheld equipment, spread spectrum systems, CDPD, and other applications in the 800MHz to 950MHz band. On-board power control provides over 30dB of control range with an analog voltage input, and provides power down with a logic "low" for standby operation. Although it is intended for class C operation, linear class AB operation can be achieved by raising the bias level. The device is self-contained with 50 input and the output can be easily matched to obtain optimum power and efficiency characteristics. Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS 0.158 0.150 0.021 0.014 -A0.009 0.004 0.392 0.386 0.069 0.064 0.050 0.244 0.230 8 MAX 0 MIN 0.010 0.008 0.060 0.054 0.035 0.016 u Package Style: Standard Batwing GaAs HBT SiGe HBT GaAs MESFET Si CMOS Features * Single 4.0V to 7.0V Supply * 1.2W Output Power * 25dB Gain With Analog Gain Control * 64% Efficiency * Digitally Controlled Power Down Mode * 800MHz to 950MHz Operation PC 1 NC 2 VCC2 3 GND 4 GND 5 GND1 6 RF IN 7 VCC1 8 BIAS 16 NC 15 RF OUT 14 RF OUT 13 GND 12 GND 11 RF OUT 10 RF OUT 9 NC Ordering Information RF2131 RF2131 PCBA High Efficiency AMPS/ETACS Amplifier Fully Assembled Evaluation Board Functional Block Diagram RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Rev B4 010417 2-99 RF2131 Absolute Maximum Ratings Parameter Supply Voltage Power Control Voltage (VPC) DC Supply Current Input RF Power Output Load VSWR Operating Case Temperature Ambient Operating Temperature Storage Temperature Rating -0.5 to +8.5 -0.5 to +4.5 570 +12 10:1 -40 to +100 -40 to +85 -40 to +150 Unit VDC V mA dBm C C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). 2 POWER AMPLIFIERS Parameter Overall Operating Frequency Range Usable Frequency Range Maximum CW Output Power Total CW Efficiency DC Current at 1.2W Output Input Power for 1.2W output Noise Power Output OFF Isolation Second Harmonic Specification Min. Typ. Max. Unit Condition T=25 C, VCC =4.8V, VPC set for POUT =+31dBm, Freq=836MHz As configured in Application schematics Depends on output matching At Max Output As configured in Application Circuit #1 In 869 - 894 MHz band (any gain or input power setting) VPC =0V, Input Power=+6dBm Depends upon external matching. Second harmonic levels directly from the IC are approximately 20 to 25dBc +30.5 55 824 to 849 800 to 950 +31 64 400 +6 -90 25 -30 +8 -85 MHz MHz dBm % mA dBm dBm/30kHz dB dBc 20 -25 Input VSWR Input Impedance <2:1 50 100 0.2 0.5 3.6 4.8 4.0 7.0 4.0 ns V V V V Specifications Operating Limits Power Down Control Turn On/Off Time VPC "OFF" Voltage VPC "ON" Voltage Power Supply Voltage Voltage 2-100 Rev B4 010417 RF2131 Pin 1 Function PC Description Power Control. When this pin is "low", all circuits are shut off. A "low" is typically 0.5V or less at room temperature. During normal operation this pin is the power control. Control range varies from about 2V for 0dBm to 3.6V for +31dBm RF output power. The maximum power that can be achieved depends on the actual output matching; see the application information for more details. Interface Schematic VCC1 PC To Bias Stages 80 2 2 3 NC VCC2 Not connected. Power supply for the driver stage and interstage matching. A shunt capacitor is required for tuning the interstage to the proper frequency. The value of this capacitor depends on the operating frequency and power level. See the application information for details. VCC2 RF IN From Bias Stages 4 5 6 GND GND GND1 Ground connection. Keep traces physically short and connect immediately to the ground plane for best performance. Same as pin 4. Ground connection for the driver stage. Keep traces physically short and connect immediately to the ground plane for best performance. It is recommended to use separate vias to the ground plane for this return path. RF Input. This is a 50 input, but the actual impedance depends on the interstage matching network connected to pin 3. An external DC blocking capacitor is required if this port is connected to a DC path to ground or a DC voltage. Power supply for the bias circuits. An external RF bypass capacitor is required. Keep the traces to the capacitor as short as possible, and connect the capacitor immediately to the ground plane. This pin is not connected internally; however it needs to be connected to ground externally. This will improve performance by reducing coupling between pins. RF Output and power supply for the output stage. The four output pins are combined, and bias voltage for the final stage is provided through these pins. The external path must be kept symmetric until combined to ensure stability. An external matching network is required to provide the optimum load impedance; see the application schematics for details. Same as pin 10. Ground connection for the output stage. Keep traces physically short and connect immediately to the ground plane for best performance. Ground connection for the output stage. Keep traces physically short and connect immediately to the ground plane for best performance. Same as pin 10. Same as pin 10. This pin is not connected internally, however it needs to be connected to ground externally. This will improve performance by reducing coupling between pins. See pin 1 schematic. 7 RF IN See pin 3 schematic. 8 9 10 VCC1 NC RF OUT See pin 1 schematic. RF OUT From Bias Stages 11 12 13 14 15 16 RF OUT GND GND RF OUT RF OUT NC See pin 10 schematic. See pin 10 schematic. See pin 10 schematic. Rev B4 010417 2-101 POWER AMPLIFIERS RF2131 Theory of Operation and Application Information The RF2131 is a two-stage device with 25dB gain at full power. Therefore, for +31dBm output power, the drive required to fully saturate the output is +6dBm. Based upon HBT (Heterojunction Bipolar Transistor) technology, the part requires only a single positive 4.8V supply to operate to full specification. Bias control is provided through a single pin interface, and the final stage ground is achieved through the large pins on both sides of the package. First stage ground is brought out through a separate ground pin for isolation from the output. These grounds should be connected directly with vias to the PCB ground plane. The output is brought out through the 4 output pins, and combined off-chip to form the RF output signal path. The amplifier operates in Class AB bias mode. The final stage is "deep AB", meaning the quiescent current is very low, around 40mA. As the RF drive is increased, the final stage self-biases, causing the bias point to shift up and, at full power, draws about 340mA. The optimum load for the output stage is approximately 10. This is the load at the output collector, and is created by the series inductance formed by the output bond wires, leads, and microstrip, and a shunt capacitor external to the part. With this match, a 50 terminal impedance is achieved. The input is matched to 50 with just a blocking capacitor needed. This data sheet defines the configuration for AMPS operation, but the output load may be modified slightly for ETACS operation. In any case the optimum load for 1.2W is the same at the device, and only the reactive elements must change to perform the transformation from 50 down to 10. The input is DC coupled; thus, a blocking cap must be inserted in series. Also, the first stage bias may be adjusted by a resistive divider with high value resistors on this pin to VPC and ground. For nominal operation, however, no external adjustment is necessary as internal resistors set the bias point optimally. VCC2 provides supply voltage to the first stage, as well as provides some frequency selectivity to tune to the operating band. Essentially, the bias is fed to this pin through a short microstrip. A bypass capacitor sets the inductance seen by the part, so placement of the bypass cap can affect the frequency of the gain peak. For ETACS, the capacitor placement is slightly different than for AMPS due to the frequency shift. This supply should be bypassed individually with 33pF or 100pF capacitors before being combined with VCC for the out2-102 put stage to prevent feedback and oscillations. The RF OUT pins provide the output power. Pins 10 and 11 should be combined externally with pins 14 and 15 with a symmetric combiner, as shown in the PCB layout. Care should be taken to ensure that the output paths are symmetric up to the point of combining. This prevents "odd-mode" cancellation from occurring wherein one side may get out-of-phase with the other, affecting efficiency and stability. Bias for the final stage is fed to this output line, and the feed must be capable of supporting the approximately 400mA of current required. Care should also be taken to keep the losses low in the bias feed and output components. DC losses in the bias choke will degrade efficiency and power. The part will operate over a 4.0V to 4.8V range. If, for example, the full power is desired at minimum voltage, then the load can be optimized at that point. This is illustrated in Application Schematic 2. At that point, the specified efficiency and power should be attainable. As the voltage is increased, however, the output power will increase. Thus, in a system design, the ALC (Automatic Level Control) Loop will back down the power to the desired level. This will occur at a less-than-optimum efficiency, since the load is optimized for minimum voltage. If the load is set up to optimize power and efficiency at nominal operating voltage, then max efficiency should be attainable there. This case is illustrated in Application Schematic 1. As the voltage drops to minimum, power will degrade, but the efficiency tends to be maintained. For nominal 31.5dBm at 4.8V setup, as the voltage drops to 4.0V, the output power drops to 30.5dBm with a constant VPC. The HBT breakdown voltage is >20V, so nominally at 4.8V there should be no issue with overvoltage. Under extreme conditions, however, which can occur in a cellular handset environment, the supply voltage could be as high as 7.5V to 8.5V. These conditions may correspond to operation in a battery charger, especially with the battery removed, which "unloads" the supply circuit. To add to this worst-case scenario, the RF drive may be at full power during transmit, and the output VSWR could be extremely high, corresponding to a broken or removed antenna. Under all of the above conditions, the peak RF voltages could well exceed two times the supply voltage, forcing the device into breakdown. The RF2131 includes overvoltage protection diodes at the output, which begin clipping the waveform peaks at approximately 15V. This protects the device's output from breaking down under these worstRev B4 010417 2 POWER AMPLIFIERS RF2131 case conditions, and provides a rugged, robust component for the system designer. High current conditions are also potentially dangerous to any RF device. High currents lead to high channel temperatures and may force early failures. The RF2131 includes temperature compensation circuits in the bias network to stabilize the RF transistors, thus limiting the current through the amplifier and protecting the devices from damage. The same mechanism works to compensate the currents due to ambient temperature variations. 2 POWER AMPLIFIERS Rev B4 010417 2-103 RF2131 Application Schematic 1 Optimized for Efficiency at 4.8V VCC VPC 10 nF VCC 100 nF 100 pF 2 POWER AMPLIFIERS 1 100 nF 2 10 nF 3 4 5 6 100 pF RF IN VCC 8 100 pF 9 7 10 4.7 pF 14 13 12 11 4.7 pF BIAS 16 15 33 pF 10 nH 2.7 nH 0.200" 100 pF RF OUT 5.6 pF 10 nH 33 pF This schematic defines the optimum configuration for maximum efficiency at 4.8V. Under these conditions, as can be seen in the data plots, the power drops at 4.0V. Over 70% power-added efficiency can be achieved at +30.8dBm with 4.8V and +8dBm input level with this implementation. 2-104 Rev B4 010417 RF2131 Application Schematic 2 Optimized for Power and Efficiency over 4.0V to 4.8V VCC VPC 10 nF VCC 100 nF 100 pF 33 pF 2 POWER AMPLIFIERS RF OUT 6.2 pF 1 100 nF 2 10 nF 3 4 5 6 100 pF RF IN VCC 8 100 pF 7 BIAS 16 10 nH 15 14 13 12 11 10 9 33 pF 4.7 pF 4.7 pF 2.7 nH 0.140" 100 pF 10 nH This application circuit differs from Application schematic 1 only slightly in the output tuning. The output shunt capacitor has been moved 0.060" closer to the device, and has increased from 5.6pF to 6.2pF. This retuning allows over +30.8dBm of output power to be achieved down to 4.0V, however a couple of percent points of efficiency are sacrificed. This implementation is recommended for some additional margin on output power. Rev B4 010417 2-105 RF2131 Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) 2 POWER AMPLIFIERS VPC C10 10 nF VCC C12 10 nF R1 0 C11 100 nF 1 2 3 4 5 C1 100 pF 6 7 8 C13 100 pF 2131400A C6 33 pF VCC 16 L2 10 nH C3 4.7 pF C8 10 F C9 100 pF BIAS 15 14 13 12 11 10 9 C4 4.7 pF L3 10 nH C7 33 pF P1-1 C2 6.2 pF L1 2.7 nH C5 100 pF 50 strip RF OUT J2 RF IN J1 VCC 50 strip P1 1 2 P1-3 3 VCC GND PC 2-106 Rev B4 010417 RF2131 Evaluation Board Layout 3" x 2" 2 POWER AMPLIFIERS Rev B4 010417 2-107 RF2131 2 POWER AMPLIFIERS 2-108 Rev B4 010417 |
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